(1) Field of the Invention
The present invention relates to a data multiplexing apparatus, a data multiplexing method and the like for multiplexing digital data such as video, audio and others for their transmission, storage and the like.
(2) Description of the Related Art
With the recent advances of digital technology, various types of services, including satellite broadcasting, CATV and video-on-demand, which are realized using digital data such as video, audio and others, have been put to practical use.
It is an important to be able to multiplex these multiple types of digital data for their transmission. As a method for multiplexing multiple types of digital data, there are Moving Picture Experts Group (MPEG) 2 Systems that follow the international standard which is jointly developed by the International Organization for Standardization and the International Electrotechnical Commission (ISO/IEC).
The MPEG2 standard includes two kinds of multiplexing systems: an MPEG2 Program Stream (PS) system suitable for storage into a storage medium or the like; and an MPEG2 Transport Stream (TS) system suitable for transmission such as broadcasting. The MPEG2-TS has a structure which allows simultaneous multiplexing of a plurality of programs into a single multiplexed stream for transmission.
The following description focuses on the conventional data multiplexing method and data multiplexing apparatus for multiplexing digital data according to the MPEG2-TS system, referring to the drawings.
FIG. 1 is a schematic diagram of the MPEG2-TS format. Digital data of video, audio and others are respectively coded and configured TS packets, each having a fixed length of 188 bytes.
The header of the TS packet includes a packet identifier (PID). One or more TS packets of video in the same program have the common PID. This is also true for the PIDs of the TS packets of audio and other digital data. In other words, one or more TS packets of audio in the same program have another common PID, and one or more TS packets of other data in the same program have still another common PID.
The header of the TS packet is followed by the data of video, audio or others, or an adaptation field. The adaptation field includes auxiliary information for multiplexing.
FIG. 2 is a diagram showing the relationship between PIDs of respective streams in a case where a plurality of programs are multiplexed simultaneously for transmission.
The PID of each stream such as a video stream and an audio stream is predetermined for each program and described in a table referred to as Program Map Table (PMT). Information on one program is described in the PMT, and a single TS includes PMTs of the number of programs.
A table in which the PIDs of the PMTs of respective programs are described is referred to as Program Association Table (PAT). A single TS includes only one PAT. The PID of the PAT is determined to be “0x0000” (a hexadecimal number).
FIG. 3 is a flowchart showing steps for reproducing a stream of video, audio and the like of a desired program from among a plurality of programs, using these PAT and PMT on the receiving end.
First, TS packets in a PAT identified by the PID of 0x0000 is detected from the inputted TS (Step S1). In the PAT, the PIDs of the PMTs of a plurality of programs are described.
After the TS packets in the PAT are detected, the PID of the PMT corresponding to the desired program is extracted from the PAT (Step S2). After the TS packets in the PMT corresponding to the desired program are extracted (Step S3), the PIDs of the streams of video, audio and the like included in the desired program are extracted from the PMT (Step S4).
Using the extracted PIDs of the streams of video, audio and the like, the TS packets with the corresponding PIDs are detected from among the received data and transmitted to respective decoders in sequence (Step S5), decoded into data of video, audio and the like, and finally reproduced as the desired program.
As described above, the MPEG2-TS standard specifies a format for allowing multiplexing of a plurality of programs into a single stream for transmission (See ISO/IEC 13818-1, “Information Technology—Generic Coding of Moving Pictures and Associated Audio: Part 1—Systems”, November 1994, for example).
Next, an MPEG2-TS multiplexing apparatus will be explained with reference to the drawings.
FIG. 4 is a block diagram of a conventional data multiplexing apparatus for MPEG2-TS. As shown in FIG. 4, this data multiplexing apparatus includes a channel buffer 801, a first address control unit 802, a local CPU 803, an output buffer 804 and a second address control unit 805.
In the channel buffer 801, inputted multi-channel MPEG2-TSs (packet streams of digital data) are stored. When receiving the packet streams, the first address control unit 802 generates, for each channel, the address in the memory of the channel buffer 801, and stores the packet streams into the memory of the channel buffer 801 by channel.
The local CPU 803 determines the order of multiplexing and outputting the packets by rewriting the time-base information and PIDs for multiplexing. The first address control unit 802 reads out, from the memory of the channel buffer 801, the inputted multi-channel packets according to the multiplexing and outputting order so as to make them into a single multiplexed MPEG2-TS, and transfers them to the output buffer 804. The first address control unit 802 reads out the packets from the channel buffer 801, and further transmits, to the second address control unit 805, a data enable signal (DATAEN) indicating the enabled section of the packets read out from the channel buffer 801.
As soon as receiving the data enable signal, the second address control unit 805 generates the memory address of the output buffer 804, and stores, into the memory of the output buffer 804, the packets transferred from the channel buffer 801. While the packets are being normally inputted into the output buffer 804, the second address control unit 805 sends, to the first address control unit 802, a ready signal (READY) indicating that the output buffer 804 is in the state of being ready for storing the inputted packets.
The first address control unit 802 is notified, upon receipt of the ready signal, that the packets are being normally transferred from the channel buffer 801 to the output buffer 804.
The second address control unit 805 outputs, at a fixed rate, the packets which are multiplexed into a single MPEG2-TS stored in the memory of the output buffer 804.
Usually, a single multiplexed MPEG2-TS needs to be outputted at a transmission rate which is compliant with the standard of a transmission line (a predetermined fixed rate). However, the operating frequency in the data multiplexing apparatus is never synchronized with the transmission rate for output, so jitter of a clock needs to be absorbed for synchronization. The output buffer 804 acts as an absorber of jitter between the operating frequency in the data multiplexing apparatus and the output transmission rate.
Since the above-mentioned memory for the channel buffer for receiving multi-channel MPEG2-TSs and for the output buffer have large storage capacity, they are required to allow high-speed transfer.
In a case where a static RAM (hereinafter referred to as SRAM) is used for this memory, it has a problem of its small storage capacity although it allows high-speed transfer. On the contrary, a dynamic RAM (hereinafter referred to as DRAM) has a problem of not allowing high-speed transfer although it has large storage capacity.
On the other hand, a synchronous dynamic RAM (hereinafter referred to as SDRAM) not only has large storage capacity but also allows high-speed transfer. Therefore, SDRAMs have been used recently as memory for various devices for high-speed writing and reading.
FIG. 5 is a conceptual diagram showing the structure of an SDRAM. The operation of an SDRAM of 16 Mbits (512 kwords×16 bits×2 banks) will be explained below as one example.
This SDRAM has two banks, each having a word length of 512 Kwords and an input/output data bus of 16-bits wide. The row address is 11 bits (2,048 rows) and the column address is 8 bits (256 columns), and each bank has a word length of 512 Kwords.
In a case where the data bus is 32-bits wide, two SDRAMs of 16-bits wide are connected in parallel for use.
FIG. 6 is a timing chart of SDRAM reading. In FIG. 6, respective signals CS, RAS, CAS and WE are low active.
A clock signal (CLK) is a signal for a synchronous clock for writing and reading data into and from the SDRAM. During reading of the data from the SDRAM, a write enable signal (WE) is kept high.
For reading of the data, a chip select signal (CS) of the SDRAM is activated first.
Next, the active command is issued for designating the bank and the row address. Generally speaking, a plurality of address setting methods can be applied to an SDRAM, but particularly in a case of high-speed reading, the address setting method as shown in FIG. 6 is applied. To be more specific, in FIG. 6, after the bank and the row address is initialized, the column address is automatically incremented one by one on every clock cycle. As mentioned above, an SDRAM allows high-speed reading of column address data, which is a burst at the designated row address of the bank, continuously in synchronism with the clock. The burst length which can be read continuously is 256 words at most in a case of the column addresses of 8 bits (256 columns).
The row address is unchanged until the data of one row is completely read. This address setting method provides higher-speed reading than the method for setting the row and column addresses at random.
After activating the chip select signal (CS), the bank and row addresses are set. The bank and the row addresses are set in the address signal (ADD [11:0]) at the same time, the row address strobe signal (RAS) is activated, and then the bank and the row address are taken into the SDRAM. Next, the column address data is set in the address signal (ADD [11:0]), the column address strobe signal (CAS) is activated, and then the default values of the column addresses are taken into the SDRAM. Since there are only 256 columns as column addresses, the higher-order 4 bits are ignored.
The column address strobe signal (CAS) is maintained active during reading of data from the SDRAM. During the column address strobe signal (CAS) being active, the column address is incremented one by one on every clock cycle (in synchronism with the clock).
Under the address control as mentioned above, the data stored in the address designated by the bank, row address and column address is outputted from the data signal (DATA [31:0]) of the SDRAM.
However, the data is not outputted immediately after the column address is set, but outputted after a lapse of CAS latency. The CAS latency is usually 2 or 3 clock cycles. To be more specific, in a case where data is read out from an SDRAM, 4 clock cycles or so are required for a period of time from activation of a chip select signal (CS) up to output of the first data, because of the necessity to set an active command, and set a column address and CAS latency.
When the data of one row is completely read and the following row is read, it is necessary to reissue the active command for designating the bank and row address so as to repeat the above-mentioned processes.
FIG. 7 is a timing chart of SDRAM writing. In FIG. 7, respective signals CS, RAS, CAS and WE are low active.
A clock (CLK) signal is a signal for a synchronous clock for writing and reading data into and from the SDRAM.
For writing of the data, a chip select signal (CS) of the SDRAM is activated first.
Next, the active command is issued for designating the bank and row address. Generally speaking, a plurality of address setting methods can be applied to an SDRAM, but particularly in a case of high-speed writing, the address setting method as shown in FIG. 7 is applied. To be more specific, in FIG. 7, after the bank and the row address is initialized, the column address is automatically incremented one by one on every clock cycle. As mentioned above, an SDRAM allows high-speed writing of column address data, which is a burst at the designated row address of the bank, continuously in synchronism with the clock. The burst length which can be written continuously is 256 words at most in a case of the column addresses of 8 bits (256 columns).
The row address is maintained unchanged until the data of one row is completely written. This address setting method provides higher-speed writing than the method for setting the row and column addresses at random.
After activating the chip select signal (CS), the bank and row addresses are set. The bank and the row addresses are set in the address signal (ADD [11:0]) at the same time, the row address strobe signal (RAS) is activated, and then the bank and the row address are taken into the SDRAM. Next, the column address data is set in the address signal (ADD [11:0]), the column address strobe signal (CAS) is activated, and then the default values of the column addresses are taken into the SDRAM. Since there are only 256 columns as column addresses, the higher-order 4 bits are ignored.
The column address strobe signal (CAS) is maintained active during writing of data into the SDRAM. During the column address strobe signal (CAS) being active, the column address is incremented one by one on every clock cycle (in synchronism with the clock).
Simultaneously with activating of the column address strobe signal (CAS), the write enable signal (WE) is activated.
Under the address control as mentioned above, the data to be inputted into the data signal (DATA [31:0]) of the SDRAM is written into the address designated by the bank the row address, and the column address.
Different from reading, in a case of writing, the data is written simultaneously with the setting of the column address, regardless of CAS latency. To be more specific, in a case where the data is written into the SDRAM, 2 clock cycles are required for a period of time from activation of the chip select signal (CS) up to writing of the first data, because of the necessity to set the active command and set the column address.
When the data is written into the following row after the data of one row is completely written, it is necessary to reissue the active command for designating the bank and row addresses so as to repeat the above-mentioned processes.
Explanation will be back to FIG. 4.
The local CPU 803 usually determines the order of multiplexing in every predetermined time period (T). It is assumed here that multiplexing processing is performed in every T=100 ms. The packet streams which are multiplexed into a single MPEG2-TS are outputted at a transmission rate which is compliant with the standard of the transmission line (a predetermined fixed rate). It is assumed here that the output transmission rate is 38.1 Mbps and the operating frequency in the data multiplexing apparatus is 30 MHz.
When performing multiplexing processing at every 100 ms, the local CPU 803 rewrites the time-base information and the PIDs. At that time, the packet streams stored in the memory of the channel buffer 801 are read and written by the local CPU 803. Therefore, for 100 ms the packet streams, which are multiplexed by the local CPU 803, need to be previously stored in the channel buffer 801.
In other words, delay of at least 100 ms occurs during a time period from inputting of the packet streams into the channel buffer 801 until multiplexing processing thereof is performed by the local CPU 803.
The second address control unit 805 outputs, at a fixed rate (38.1 Mbps), a single multiplexed MPEG2-TS stored in the memory of the output buffer 804. Since the output rate compliant with the standard of this transmission line is not synchronized with the operating frequency (30 MHz) in the data multiplexing apparatus, the output buffer 804 is required for absorbing jitter of a clock.
Since the local CPU 803 performs multiplexing processing at the rate of 100 ms, the packets for at least 100 ms need to be stored in the output buffer 804 in order to avoid underflow or overflow of the output buffer 804. Usually, the output buffer 804 is controlled so as to store packets for 100 ms+α to 200 ms+α.
In other words, delay of more than 100 to 200 ms occurs in the output buffer 804.
As mentioned above, the delay of the packets in the data multiplexing apparatus is around 200 to 300 ms in total, namely, 100 ms for multiplexing processing in the local CPU 803 and 100 to 200 ms in the output buffer 804.
As described above, the conventional data multiplexing apparatus uses a channel buffer for data input and data multiplexing and further uses an output buffer for outputting a single multiplexed packet stream at a transmission rate compliant with the standard of the transmission line, so the delay of the packets in the data multiplexing apparatus is 300 ms or so.
Since there is no particular problem in a case of on-demand viewing of a video signal and an audio signal because delay of 300 ms or so occurs only when the viewing starts.
However, since the conventional data multiplexing apparatus also performs the data multiplexing processing on a private data signal as well as video and audio signals, delay of 300 ms occurs every time it transmits or receives the data.
Particularly in a case where private data is distributed by storing, into the private data signal, IP packets including the Internet information for interactive access to each page, it becomes a problem if delay of 300 ms occurs on every transmission or reception of data (i.e., on every interaction of a user). In other words, this type of delay may cause time consumption of dozens of seconds for displaying the user-requested page on the Internet. Therefore, it is preferable to restrain the delay of the private data signal in the data multiplexing apparatus within dozens of ms.